Low-power design of 8-b embedded CoolRisc microcontroller cores

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Publication Details

Output type: Other

Author list: Piquet C, Masgonty JM, Arm C, Durand S, Schneider T, Rampogna F, Scarnera C, Iseli C, Bardyn JP, Pache R, Dijkstra E

Publisher: Institute of Electrical and Electronics Engineers

Publication year: 1997

Journal: IEEE Journal of Solid-State Circuits (0018-9200)

Volume number: 32

Issue number: 7

Start page: 1067

End page: 1078

Number of pages: 12

ISSN: 0018-9200

eISSN: 1558-173X

Languages: English-Great Britain (EN-GB)

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Open access status: closed

Abstract

Low-power and low-voltage embedded microcontrollers are required more and more for portable applications. Power reduction can be addressed at the software level as well as at the architecture level while searching to reduce the number of executed instructions for a given task. An 8-b RISC-like pipelined microcontroller family is presented achieving one clock per instruction. It is compared to various architectures of existing 8-b microcontrollers. According to an efficiency model taking into account the architecture as well as the number of registers, the presented 8-b microcontroller cores provide four to ten times better performances than existing microcontrollers. On one hand, the operating frequency can be reduced to execute a given task in the same execution time. On the other hand, delivering 10 MIPS performance, more than 2000 MIPS/W can be achieved at 3 V.

Keywords

computer architecture, integrated circuit design, micropower, microprocessors, pipeline processing

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