AN 8-BIT MULTITASK MICROPOWER RISC CORE
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Publication Details
Output type: Journal article
Author list: PEROTTO JF, LAMOTHE C, ARM C, PIGUET C, DIJKSTRA E, FINK S, SANCHEZ E, WATTENHOFER JP, CECCHINI M
Publisher: Institute of Electrical and Electronics Engineers
Publication year: 1994
Journal: IEEE Journal of Solid-State Circuits (0018-9200)
Volume number: 29
Issue number: 8
Start page: 986
End page: 991
Number of pages: 6
ISSN: 0018-9200
eISSN: 1558-173X
Languages: English-Great Britain (EN-GB)
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Open access status: closed
Abstract
This paper describes a multitask micropower RISC core. A hardware scheduler handles up to four separate tasks in a pseudo-parallel way. Task or context switching is performed at the instruction level and does not need additional instructions. In a 1.5-V low-power 2-mum technology the core area is 5-6 mm2, depending upon the global routing of the complete ASIC. Measured power consumption is 0.2 muA/kHz at 1.5 V with a low-power 8-K word ROM and a 256-byte RAM.
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